System design is a complex process, not only with the use of ICs, but also a lot of details to consider. This article uses a high-fidelity music playback system as an example to introduce how to select chips to build a system that meets market needs.
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The modern integrated circuit industry has been strictly following the rapid development of "Moore's Law". The faster and faster the chip develops, the lower the requirements for the software system. Speed ​​is everything now, whether it's chip speed, software development speed, or time to market. But is it enough to have a chip? Let's start with a relatively simple high-fidelity music playback device to see how we need to implement one such system using commercially available ICs.
Audio system requirements for processor chips
From the point of view of signal processing and chip design, the principle of audio system is not complicated. Therefore, many semiconductor manufacturers do not seem to be able to look at audio products, but to chase some products with high technical content such as high-definition video processing. . When I designed this high-fidelity music playback system, I used to pass the design department of different domestic IC design companies. The answer was to smash the past with a "very simple and no problem", but in fact After the system is made, it often finds that the effect is not satisfactory. It can be said that in the development of this system for a few years, due to the problem of chip selection, the hardware performance bottleneck has suffered.
The following are our specific requirements for the processor chip: 1. The speed should be above 400MHz, it is best to decode the APE C4000 code rate; 2. Need to support USB 2.0 Host/SATA/SD card; 3. Need support network; 4 With 128MB or more RAM, the bigger the better; 5. 256MB or more NAND Flash; 6. Support I2S multi-output and support Slave clock, support up to 768KHz sampling rate, and up to 32-bit output; 7. Best Have audio data post-processing capabilities; 8. Excellent performance clock circuit and DAC.
The core speed that the chip can run has a crucial impact on the decoding efficiency. For example, audio lossless compression APE C5000 decoding method has high requirements on the processor. Take Intel ATOM 1.6G netbook as an example, which decodes 192k/C5000 two channels. Music can't be played continuously, let alone the ordinary embedded system? Therefore, only a lower bit rate can be handled. Lossless compression is not the same as MP3. It needs to restore a completely consistent data stream. Processor performance determines the efficiency of decoding, so too low core frequency is not suitable for this work.
USB 2.0 has a very high hardware requirement, and PHY compatibility is a big problem, and the efficiency of data flow is second. Similarly, SD card interface compatibility is also a very headache for domestic chips. The demand for SATA puts the peripheral peripheral speed of the processor to a higher position. After all, not everyone can do 1.5G/3G PHY.
System operation depends on the programs stored in NAND Flash, but NAND Flash is growing faster than processors. When NAND Flash was defined, ECC was designed outside, and the processor was always behind NAND Flash for a period of time. Therefore, when NAND Flash is transformed, the manufacturer will not be able to ship because of the lack of chips in the market or need to pay for it at a high price. On the other hand, with the improvement of RAM, the cost is getting lower and lower, resulting in a gradual reduction in high-cost SDRAM. Therefore, the processor using the old memory is inherently insufficient, and the system BOM cost is higher than the system using the new RAM. Therefore, the processor needs to support multiple boot modes, not limited to NAND Flash. At the same time, RAM should conform to the current mainstream computer and use DDR2/DDR3 and other memory, so that it can achieve low cost and high profit.
The last and most important issue is the I2S of the audio system. Regardless of where the data stream flows in, it needs to be output from I2S, and this data stream does not allow any data errors and churns under any circumstances, unless the processor is not fast enough. At the same time, the internal PLL of the processor can't generate the I2S clock we need, so the external clock is inevitable, and the Slave I2S interface is also essential. In fact, I2S encountered the most problems in our development process, such as inaccurate synchronization, left and right channel inversion at the beginning of playback, irregular left and right channel inversion during playback, and frame loss of data output. The technical parameters of the output are such that the design requirements cannot be met.
In the course of product design in the past few years, the detour is due to the fact that the details of the chip are not known. Because any manufacturer's development system does not directly indicate whether it can support high-definition music formats, the maximum output of music output is supported, and it is impossible to directly evaluate whether its platform can achieve the performance indicators we need, so we must according to our needs. The I2S output circuit is adjusted. In order to evaluate the system, we had to do a lot of design work (including hardware and software) before we could carry out the evaluation.
Chip selection needs to measure multiple performance parameters
In the design process, we chose Samsung's chip, and also chose domestic chips, but they have to give up because of various problems, and finally decided the current plan. Samsung's chip I2S output is not enough, the type of NAND Flash supported is limited, SDRAM unit cost is high, USB host until its ARM11 products can not keep up with the required speed, so we gave up after the first selection. Later, I chose the domestic platform, because the depth of the I2S FIFO is not enough, causing frame loss. In addition, due to the problem of the USB PHY, the compatibility of the flash disk is very poor, and the upgrade platform is not solved. The compatibility of the SD card due to software problems is not Well, the more deadly problem is because the system is unstable, the processor can't be reset normally, or the NAND Flash loses data for a while after running for a while, and finally it can't be used.
After the product finally won the details, after trying all kinds of products with hard wounds, we finally had to give up the domestic chips and chose the products of foreign manufacturers. From the hardware system of the A manufacturer, the result can be that the hardware details are quite good. We tested the chip to find that the consistency was high and the system margin was well designed. The nominal 375MHz chip can basically overclock to 572MHz under the condition of non-highest core voltage, which is 50% higher than the nominal frequency. At the same time, the DDR2 clock is overclocked by 60%, and the performance is good. From the register design, many are designed according to the data structure of the Linux system, so as long as you are familiar with the software, it is easy to get familiar with the hardware.
In the large-scale data throughput part, the A manufacturer uses the link DMA. This detail perfectly guarantees the continuity of the output data stream, and ensures that the most important I2S data output will not drop frames. When we tested, we decompressed the local data through the SD card while decoding, and there was no frame loss when the CPU was fully loaded. It can be seen that the hardware of the A manufacturer is strong.
Here we analyze why the frame is dropped. In fact, most of the systems complete the transmission of the data stream. The data flow of the audio decoding is to read the original code stream from the SD card and other media, and then send the I2S output after decoding by the CPU. This process involves the transmission of important data. In the process of going to RAM and then from RAM to I2S, these data streams are all done by DMA, and the bottleneck is in the process of DMA switching. The Linux file system is cached by the system, and the timing requirements are not high. I2S requires continuous data, which is closely related to the I2S FIFO. If the system does not automatically switch the buffer, the CPU is required to intervene, and the CPU The interrupt response time will seriously affect the continuity of the data. For example, the FIFO of I2S is 32 data. If the LRCK of I2S is 192kHz, the maximum interrupt time that can be given to the CPU is 32/2/192kHz=83μs, and according to the interrupt mechanism, it is generally half of the FIFO to apply for interrupt. Then the time is less than 50μs, which is basically unable to meet the demand in ordinary Linux systems, so frame loss is inevitable. When the IC manufacturers design the indicators are designed according to the hardware index of 96kHz, of course, can not meet the requirements of high-end systems. A manufacturer's automatic DMA chain does not require the CPU to switch data, but the software divides 2 or more pieces of data (Ping pong buffer) to allow the DMA to automatically switch, thus perfectly guaranteeing the continuity of the output data. For the sound system, as long as the I2S is lost, it will be detected immediately, and it will not be detected by the instrument. Therefore, if this detail is not in place, it will not be able to go to the market.
In addition, the hardware of the A manufacturer includes the SATA interface and the USB 2.0 host/SD card support with impeccable compatibility and speed. What's more, the small ARM9 chip also has EMAC and two small single-chip microcomputers. Each speed is half of the system clock speed. This small single-chip microcomputer can achieve far more functions than ordinary MCUs. If the CPU speed is not enough, you can also choose a pin-compatible chip with floating-point DSP. The computing power of this DSP is equivalent to the computing speed of the same ARM9 above 2G, which has a vital performance improvement for data back-end processing. The A manufacturer's film also provides the TF card startup function, which can perfectly avoid the problems brought by the development of NAND, and solve the problem of the startup speed of the file system established by Linux in NAND.
Let's talk about the clock circuit here. Since it needs to support the sampling rate of 32K~192K, it must be able to generate the corresponding clock, and the jitter is required to be lower than 50ps (the built-in PLL clock of the processor is generally above 200ps). For the DAC, many domestic chips integrate the DAC into the CPU because of the low cost of integration, but this can not improve the performance. For example, the THD+N can only be up to 90dB, and the current world-class DAC has its THD+N. Amazing -120dB while providing a dynamic range of 135dB. This high performance has extremely strict requirements on the entire system design, so the price of similar foreign products is no less than 4,000 US dollars. Another key point in the design of the hardware system is the PCB trace.
In terms of software, the system needs to cover dozens of optimized audio decoders. The decoded output digital signals are processed by DSP. In addition, FPGA Verilog software programming, network UPNP protocol control, file sharing, remote playback/control, etc. The scope of the agreement is quite extensive. At present, there are basically no suppliers in the country that can carry out related design and production.
summary
The audio system is a combination of typical low-frequency analog signals and high-frequency digital signals, so there are only a handful of manufacturers that can be done internationally, and even rare in China. After more than three years of research and development, the system has finally reached the international middle and upper level. The product sense is comparable to that of the international first-line brand Linn Akurate DS. Due to the reasonable design of the system, the speaker in the strict listening environment and the market price are at 12 The DAC A/B comparison of a well-known European brand of around 10,000 yuan makes the listening experience even better.
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