The world's leading RapidIO IP solution
RapidIO was originally developed by the United States Mercury Computer Systems (American Mercury Computer Systems) as its bus technology for its computationally intensive signal processing system. RapidIO is a packet switching structure. It was originally developed to connect the chips on the circuit board and the circuit boards in the chassis. RapidIO uses packet switching technology in the network processor (NPU) and central processing unit (CPU) The communication with the digital signal processor (DSP) has high-speed, low-latency, stable and reliable interconnectivity. It was later adopted by Motorola and other semiconductor companies. In order to promote its application, Mercury has initiated the establishment of RapidIO Trade Association and VITA International Trade Association. Mercury has deservedly become a core member of the association. At present, RapidIO has become an open standard, and major semiconductor companies in the world have successively launched Related products based on RapidIO technology, systems based on RapidIO communication architecture technology such as ATCA, VITA series (VITA41 is VXS, VITA46 is VPX, VITA48 is REDI), CPCI and other systems have been widely used in telecommunications, defense, medical and other industries.
RapidIO can provide bandwidth of more than 10Gbps (RapidIO 2.0 specification can provide 100Gbps bandwidth), all its protocols are implemented by hardware, and have nothing to do with software. RapidIO simplifies the definition of endpoints, and its size is similar to that of PCI-X endpoints. It can be installed in FPGAs, occupying only a small part of the chip area, and the rest can be reserved for other uses. Many RapidIO ports can be placed in the newly designed I / O chip, so the dedicated switch chip can be simplified. Because it is a point-to-point communication, it can achieve more synchronous transmission than a multi-point bus, and the transmission capacity can continue to improve with future performance improvements.
The main features of RapidIO are extremely low latency (nanosecond level) and high bandwidth, much lower than PCI, PCI-X, PCIe and Infiniband latency, and it is easy to implement and PCI, PCI-X, PCIe, FPDP, Ethernet and other bridges are suitable for high-speed data transmission between chips and chips, boards and boards, systems and systems.
As a pioneer in computing heterogeneous switching structures, Mercury has unique system and application experience to provide the best RapidIO system technical support and consulting services for user needs. These solutions have extremely high processing performance, I / O capacity and data bandwidth, and can meet the application of the new generation of images and digital signals, including defense electronics, medical imaging and civilian markets.
RapidIO IP products comply with industry standards, use packet interaction technology, and have high performance. The communication between the network processor (NPU), central processing unit (CPU), and digital signal processor (DSP) has high-speed and reliable interconnectivity . IP products can meet the needs of standardization of transmission performance, high-speed transmission and reliable interconnection, and focus on promoting the network, embedded and storage markets. RapidIO can carry out chip-to-chip, board-to-board and system-to-system communication, with a transmission speed of 10Gbps or higher.
RapidIO IP chips should be born in the increasingly mature RapidIO market. The chip is independent of the physical layer design, processing tools, and target technology. The chip can be used in a variety of solutions, including endpoints and switching applications.
Mecury RapidIO IP can be used for application specific integrated circuit (ASIC) and field programmable gate array (FPGA) development. The product can be reused, has been optimized for performance and reliability, and can be used in a variety of solutions, including endpoints and switching applications. Mecury RapidIO IP has a clearly defined host structure, which simplifies the design of its integration with other different host interfaces.
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