Analysis of the roles of directories and files created by the xilinx IP creation wizard

The core of the e-family network tips : What are the directories and files created by the xilinx IP creation wizard? This is caused by the error ERROR: HDLCompiler: InstanTIaTIng from unknown module.

The XPS is used to create and import the IP Wizard (referred to as ipwiz). The default source files are only the "userlogic.v" in the hdl/verilog directory and the "ipname.vhd" file in the hdl/vhdl directory. When our design becomes more complicated and requires more design files such as .v, .vhd, .ngc, etc. and multiple modules/entities, the compiler will prompt for the module error if no settings are made. Hint: ERROR: HDLCompiler: InstanTIaTIng from unknown module. How can I get the compiler to find all our design files and modules?

For example, these days I made a character VGA IP core, the IP name is axi_vga, and the design file structure in the hdl directory is as follows:

Design file structure in the hdl directory

Except for the user_logic.v and axi_vga.vhd files generated by ipwiz, other design files are added later. After importing the IP into the ARM PS system, perform DRC check, and then run bit generation, the following error message will appear:

After importing the IP into the ARM PS system, perform the DRC check, and then run the bit generation, the following error message will appear.

The error is not limited to this one. Other design files such as CGROM.v, DPBRAM.v, user_logic.v, and DCM1.vhd all have errors in finding the module. This is very strange, because the design files are in the same directory, why the compiler can not find it?

In order to know the cause of this error and solve it, you need to know more about the directories and files generated by ipwiz.

There are three directories generated by ipwiz, we analyze them one by one.

1, hdl directory

There are all design files in the hdl directory, including .v and .vhd. Because the AXI bus interface modules are described in the VHDL language, xilinx subdivides the verilog and vhdl folders to store the design files in order to facilitate the management of different types of design files.

2, devl directory

When using the ipwiz wizard, there is an option if you need to produce a test ise project. If you choose it, this directory will produce the ise project for testing. If not selected, the devl directory will only keep a few log files.

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