Voltage drop (IR) on the VDD network and ground bounce on the VSS network can affect the overall timing and functionality of the design, and ignoring their presence may result in chip design failure. Large currents in the power grid can also cause electromigration (EMI) effects that can cause metal line performance degradation in the power grid during the normal life of the chip. These adverse effects will ultimately result in costly field failures and severe product reliability issues.
IR grid drop and ground bounce of the power grid
The cause of the IR drop on the VDD network is that the operating current of the transistor or gate flows out of the VDD I/O pin through the RC network of the power grid, causing the VDD voltage to reach the device to drop. Ground bounce is similar. Current flows back to the VSS pin through the RC network, causing the VSS voltage to reach the device to rise. More sophisticated design techniques and next-generation design techniques allow new designs to take greater risks in terms of IR drop or ground bounce. The IR drop on the power grid primarily affects timing, which reduces the drive capability of the gate and increases the latency of the entire path. Under normal circumstances, a 5% drop in the supply voltage will increase the delay by more than 15%. The time delay of the clock buffer is more than doubled due to the IR drop. Such a delay increase would be very dangerous when the clock offset is within 100 ps. Imagine what happens to this unexpected delay on the critical path of a centralized configuration. Obviously, the performance or functionality of the design will become unpredictable. Ideally, to improve design accuracy, the timing calculation must take into account the worst-case IR drop.
Power grid analysis methods mainly include static and dynamic methods.
Static power grid analysis
Static power grid analysis provides comprehensive coverage without additional circuit simulation. Most static analysis methods are based on the following basic concepts:
1. Extracting the parasitic resistance of the power grid;
2. Establish a resistance matrix of the power grid;
3. Calculate the average current of each resistor or gate connected to the power grid;
4. Depending on the physical location of the transistor or gate, the average current is distributed into the resistor matrix;
5. Apply the VDD source to the matrix on each VDD I/O pin;
6. The current and IR drop across the resistor matrix are calculated using a static matrix solution.
Since the static analysis assumes that the decoupling capacitance between VDD and VSS is sufficient to filter out the IR peak or the dynamic peak of the ground bounce, the result is very close to the dynamic conversion effect on the power grid.
The main value of static analysis is reflected in simple and comprehensive coverage. Since only the parasitic resistance of the power grid is required, the amount of extraction is very small. And each transistor or gate provides an average load on the power grid, so the method can cover the power grid completely, but its main challenge is accuracy. Static analysis does not consider local dynamic effects and package conduction effects (Ldi/dt). If there are not enough decoupling capacitors on the power grid, both will lead to further IR drop and ground bounce.
Dynamic power grid analysis
The dynamic power grid analysis method not only requires the extraction of the parasitic resistance of the power grid, but also requires the extraction of parasitic capacitance, and the dynamic circuit simulation of the resistor RC matrix is â€‹â€‹completed. Typical steps for dynamic power grid analysis are:
1. Extract parasitic resistance and capacitance of the power grid;
2. Extract parasitic resistance and capacitance of the signal network;
3. Extract the design netlist;
4. Generating a circuit netlist based on the extracted parasitic resistance, capacitance value, and netlist;
5. The circuit simulation is performed according to the simulation vector set, mainly simulating the dynamic conversion of the transistor or the gate and the influence of the conversion on the power grid.
The main value of dynamic analysis is reflected in its accuracy. Since the analysis is based on circuit simulation, the IR drop and ground bounce results will be very accurate, taking into account local dynamic effects and package conduction effects.
But the challenges of dynamic analysis are also very difficult, because:
1. Parasitic extraction requirements are very high because of the need to extract the resistance and capacitance of the power grid and (at least) the capacitance of the signal network.
2. There are many objects in the circuit simulation, which will make the circuit simulation engine work at full load.
3. The vector set used as the excitation signal plays an important role in determining the output quality. If a complete set of test vectors is not used, the results will be questionable because some parts of the power grid may not be emulated.
4. Finally, due to the many considerations of a single power grid, power grid analysis based on full dynamic simulation will be difficult to accommodate further increases in design size.
Many power grid analysis methods that pursue dynamic effects must resort to RC compression techniques to manage large amounts of simulation data. However, this is in contradiction with the main value of dynamic analysis, high precision. The RC compression of the power grid can result in reduced accuracy of the analysis results and even mask real EMI problems.
Electromigration and full-chip EMI analysis
The electromigration of the power grid is a direct current phenomenon caused by the average current flowing through the metal lines and the vias. This is another important issue in the design of deep submicron power grids. Large current densities and narrow line widths can cause EMI, and failures caused by EMI can be catastrophic. These faults usually occur at the user, and the chip is already installed on the substrate in the system. If there is a problem, the design may be recalled.
Although EMI may cause open or short circuits in the power grid, the most common effect is an increase in the resistance value in the power grid path, which causes IR drop or ground bounce, which affects the timing of the chip. This is why a design was originally working properly and conforming to specifications, but then failed. The guiding basis for EMI design is the average current level, which ultimately depends on the signal line capacitance.
Therefore accurate EMI prediction requires correct capacitance information. In addition, since the metal lines in the design will vary in height and the metal has different levels of material properties, each metal layer will have different failure criteria, so the only way to determine all areas of the chip that have potential EMI problems is to do so. Full chip analysis.
The industry's commonly used Black law predicts the mean time between failures of metal wires. The main parameter is the average current density J shown next to the metal lines. The more accurate the average data, the better the MTTF estimate. In order to get the most accurate data information, it is often necessary to use a large number of vectors in the design. At the same time, the average current of each metal line must be measured and then divided by the width and thickness of the line. This is obviously impossible to construct a chip, and it cannot be implemented by circuit simulation.
Another way to replace expensive transistor-level simulations is to use gate-level or higher-level tools to obtain the average current that appears in the form of trigger data from the activity information. Trigger data is actually just the number of times a gate completes high and low transitions during the simulation cycle of thousands of clocks. The activity information can be obtained by dividing these trigger data by the number of clock cycles. For example, the core of a memory circuit may be 0.02% active and a data path may be close to 5%. These factors can be converted to average current information for transistors connected to the power grid.
Of course, the designer must judge the average current flowing across the power grid to assess the reliability risk of a given design. It is not enough to judge the average behavior of the isolated modules, because the modules may only work periodically in a full-chip process. In addition, even changes to a portion of the power grid can have a global impact. Data compression is also unusable because data compression itself can mask some real EMI problems. Therefore, unless the entire chip is fully verified as an entity, there is still a risk of insufficient EMI prediction accuracy. Any tool used for this purpose must have the ability to analyze millions of resistor networks.
Power Grid Analysis is now a key part of the design verification process. The design of IC power distribution systems has become extremely complex due to IR drop, ground bounce, and EMI. Earlier, DRC, LVS, and manual calculations of the power grid ensured a perfect power grid design, and the effort to design the power grid was considered an acceptable solution at the time. In today's fiercely competitive market, too much consideration of the power grid will lead to a decline in yield, and the design is not competitive, and the lack of consideration can lead to failures, repeated and costly field failures - after all, Both are the best.
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